`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:10:19 12/05/2024
// Design Name:   Main
// Module Name:   C:/CYH/ISE/6/Lab6/Test02.v
// Project Name:  Lab6
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Test02;

	// Inputs
	reg CP1;
	reg Sd_1;
	reg Rd_1;
	reg J1;
	reg K1;
	reg CP2;
	reg Sd_2;
	reg Rd_2;
	reg J2;
	reg K2;

	// Outputs
	wire Q1;
	wire Q1_;
	wire Q2;
	wire Q2_;

	// Instantiate the Unit Under Test (UUT)
	Main uut (
		.CP1(CP1), 
		.Sd_1(Sd_1), 
		.Rd_1(Rd_1), 
		.J1(J1), 
		.K1(K1), 
		.Q1(Q1), 
		.Q1_(Q1_), 
		.CP2(CP2), 
		.Sd_2(Sd_2), 
		.Rd_2(Rd_2), 
		.J2(J2), 
		.K2(K2), 
		.Q2(Q2), 
		.Q2_(Q2_)
	);

	initial begin
		// Initialize Inputs
		CP1 = 0;
		Sd_1 = 0;
		Rd_1 = 0;
		J1 = 0;
		K1 = 0;
		CP2 = 0;
		Sd_2 = 0;
		Rd_2 = 0;
		J2 = 0;
		K2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

